The present invention relates to a method of flattening the surface of a semiconductor device by polishing through the use of colloidal silica slurry.
In recent years, as the miniaturization of semiconductor elements constituting semiconductor integrated circuits proceeds, it has become necessary to form patterns with a dimension of 1 .mu.m or less. For example, in order to form aluminum wiring patterns with a pattern width of 0.4 .mu.m to construct a 64 Mb DRAM, a photolithography process including the following steps using a reduction projection exposure apparatus is performed:
(a) A step in which an aluminum film is grown over the entire area of a silicon substrate using sputtering equipment; PA1 (b) A step in which, after applying resist to the aluminum film, the aluminum film is exposed to light using I-radiation reduction projection exposure equipment (wavelength=365 nm); PA1 (c) A step in which a resist pattern 0.4 .mu.m wide is formed by developing; and PA1 (d) A step in which the aluminum film is etched by dry etching using the resist pattern as a mask to form the aluminum wiring patterns.
The practical resolution R of the resist pattern obtained by the photolithography process using the reduction projection exposure equipment and the focus margin M for an offset on the surface to be exposed are given by equations (1) and (2), respectively: EQU R=0.6.times..lambda./NA (1) EQU M=0.5.times..lambda./NA.sup.2 ( 2)
"NA" is the aperture value of the optical system, and ".lambda." is the wavelength of light used for exposure. From equation (1), since the practical resolution R of the resist pattern increases in proportion to the wavelength .lambda. of light used for exposure but increases in reverse proportion to the aperture value NA of the optical system, in order to form a fine resist pattern, it is necessary to employ a light source having a shorter wavelength and employ an optical system having a higher aperture value. However, from equation (2), since the focus margin M for the offset on the surface to be exposed increases in reverse proportion to the square of the aperture value NA of the optical system, as the aperture value NA of the optical system increases, the focus margin M for the offset on the surface to be exposed decreases sharply. As a result, since the surface of an actual semiconductor device has various offsets of different sizes and different heights depending upon underlying patterns such as aluminum wiring patterns, when the focus margin M decreases, it becomes difficult to form another fine resist pattern over the underlying patterns. Further, though not described in detail here, as the miniaturization proceeds, it becomes increasingly difficult to etch by dry etching a thin film (for example, a sputtered aluminum film) formed on a steep offset which has an edge having a shape similar to a vertical wall. In this manner, the reduction of offsets existing on the surface of a semiconductor device in which various underlying patterns are formed over the semiconductor substrate (that is, flattening the surface of the semiconductor device) becomes a significant subject as the miniaturization proceeds from a 64 Mb DRAM to a 256 Mb DRAM and further to a 1 Gb DRAM.
Thus, a reflow flattening method and an etching back flattening method, the typical flattening methods of the prior art for the surface of a semiconductor device, are first described briefly, following which a prior art flattening polishing method which is specifically related to the present invention is described in detail.
(A) Reflow Flattening Method
In a flattening process in which a BPSG (Boro-phospho-silicate Glass) film is employed as a reflow film, a BPSG film 4 is formed on underlying convex patterns 2 such as polycrystalline silicon stacked capacitor patterns shown in FIG. 1. The growth of the BPSG film 4 is performed in most cases by the atmospheric pressure CVD method using ozone (O.sub.3)--tetramethoxysilane (TEOS)--trimethylphosphate (TMP)--trimethylborate (TMB) as gas sources because it is superior in step coverage (Numazawa et al., Monthly Semiconductor World, November, 1989, pp. 74-77). Thereafter, the BPSG film 4 is heated to about 900.degree. C. and reflowed as shown in FIG. 2. The mechanism by which the BPSG film 4 is reflowed at high temperature is explained by the phenomenon of mass transfer in which offsets on the surface of the BPSG film 4 are flattened so that the surface free energy may be minimized (W. Kern et al., Solid State Technology, June, 1985, pp. 171-179).
The most significant advantage of the reflow flattening method is that the process is easy. However, since a high-temperature heat treatment is necessary in order to reach reflow conditions, when the miniaturization proceeds to the deep submicron order, there may be an adverse influence on the characteristics of transistors existing in a layer below the BPSG film 4. Further, the reflow flattening method naturally cannot be applied as the method of flattening the surface of an interlayer insulating film when multilayer metal wiring lines are formed over a semiconductor substrate. Furthermore, although the surface in an area R shown in the central portion of FIG. 2 in which the underlying convex patterns 2 are concentrated can be flattened, an offset at a boundary location between the area R and a perimetric area in which no underlying convex pattern 2 exists or an offset formed by an isolated underlying convex pattern 2' shown at the right end in FIG. 2 cannot be removed effectively. As a result, a height h of the offsets after the reflow shown in FIG. 2 is substantially equal to a height h.sub.O of the initial offsets shown in FIG. 1.
(B) Etching Back Flattening Method
The etching back flattening method makes use of the transfer of a smooth surface topology of an applied film applied over a semiconductor substrate by spin coating (Nikkei Microdevice, June, 1988, pp. 33-46). According to the etching back flattening method, as shown in FIG. 3, a silicon oxide film 13 is formed by the CVD method over underlying convex patterns 12 such as aluminum wiring patterns which are formed over a device layer 11. Thereafter, as shown in FIG. 4, an applied film 19 such as a resist or spin-on-glass (SOG) having sufficiently smooth surface topology to moderate offsets present on the surface of the silicon oxide film 13 is formed on the silicon oxide film 13 by the spin coating (L. E. Stillwagon et al., Journal of Electrochemical Society, Vol. 134, No. 8, p. 2030, 1987). Thereafter, the silicon oxide film 13 and the applied film 19 are etched by dry etching under the conditions of an etching gas which equalizes the etching rate of the silicon oxide film 13 and the applied film 19. As a result, the smooth surface topology of the applied film 19 is transferred to the surface of the silicon oxide film 13 as shown in FIG. 5.
Since the etching back flattening method does not require a high-temperature heat treatment, it is advantageous in that it can also be applied as a method for flattening the surface of an interlayer insulating film when multilayer metal wiring lines are to be formed over a semiconductor device. With the etching back flattening method, however, since the silicon oxide film 13 and the applied film 19 are etched simultaneously, the ratio between the thickness of the silicon oxide film 13 and the thickness of the applied film 19 always varies for a time immediately after starting the etching and immediately before ending the etching. Accordingly, the etching back flattening method has a problem in that it is difficult to always select the conditions of the etching gas which will equalize the etching rates of the silicon oxide film 13 and the applied film 19. Further, even if the etching back flattening method is used, an offset at a boundary location between an area R at the central portion of FIG. 3 in which the underlying convex patterns 12 are concentrated and a perimetric area in which no underlying convex pattern 12 is present or an offset formed by an isolated underlying convex pattern 12' cannot be removed effectively, and problems similar to those encountered in the reflow flattening method described above cannot be solved. As a result, the offsets of height h substantially equal to height h.sub.O of the initial offsets shown in FIG. 3 remain.
(C) Flattening Polishing Method
As described above, when the surface fluidity of a BPSG film or a spin coated film is utilized as in the reflow flattening method or the etching back flattening method, an offset at a boundary location between an area in which underlying convex patterns are concentrated and a perimetric area in which no underlying convex pattern is present or an offset formed by an isolated underlying convex pattern cannot be removed effectively. In other words, in order to flatten the entire surface of a semiconductor device, the only remaining method is to mechanically polish the surface of the semiconductor device to remove all convex patterns present on the surface of the semiconductor device. The widely known polishing techniques involve embedding an oxide film in a recessed portion of the surface of a silicon device (W. S. Liudenberger et al., 1991 VLSI Technology Symposium Technical Digest, p. 89, and Davari et al., IEDM Technical Digest, IEEE, pp. 61-64, 1989), as represented by the mirror surface processing technique for a silicon device through the use of colloidal silica slurry (Arno Henry Haazok et al., Japanese Patent Application No. 1974-13665) or the trench element separate embedded oxide film layer formation.
However, in recent years, an attempt to apply a polishing technique to flattening convex patterns present on the surface of an interlayer insulating layer has been reported (R. R. Uttecht et al., Proc. 1991 IEEE VMIC Conference, pp. 20-26, 1991). According to this method, metal wiring patterns 28 are formed over a silicon substrate 20 as shown in FIG. 6A. Thereafter, an oxide film 29 is grown over the metal wiring patterns 28 by the plasma CVD method as shown in FIG. 6B. In this instance, since the metal wiring patterns 28 are present, convex portions 25 are produced on the surface of the oxide film 29. The surface of the oxide film 29 is pressed under a load against a rotary polishing surface block on which a polishing pad is applied while colloidal silica slurry used as working liquid is dropped onto the surface of the oxide film 29. In this instance, since the working pressure at the convex portions 25 is locally higher than that at a flat portion, the working rate at the convex portions 25 is relatively high. As a result, the convex portions 25 are scraped so that the surface of the oxide film 29 is flattened. Thereafter, via holes 21 are formed in the oxide film 29 as shown in FIG. 6C, and then, new metal wiring patterns are formed over the oxide film 29.
In this manner, the widely known conventional flattening polishing method involves the mechanical removal of convex portions existing on the surface of an insulating film. Further, since the flattening polishing method is a low-temperature process which requires no high-temperature heat treatment, it can be applied also as a flattening method for an interlayer insulating film when multilayer metal wiring patterns are to be formed over a semiconductor substrate. Accordingly, the most significant advantage of the flattening polishing method is in that it is a comparatively inexpensive and easy process which requires neither dry etching equipment nor achievement of severe etching conditions.
However, as described below, the conventional flattening polishing method is subject to three limitations: a pattern size dependency of flattening working characteristics, a dispersion in a working amount of a substrate in its plane, and a metal pollution to a device layer.
First Subject: Pattern Size Dependency of Flattening Working Characteristics
Flattening the surface of an insulating film by polishing makes use of the phenomenon that the working pressure locally increases at a convex portion existing on the surface of an insulating film. For example, where a plurality of metal wiring patterns 38 having an equal width are formed over a silicon substrate 30 with a device layer 31 interposed therebetween as shown in FIG. 7A, when an oxide film 39 formed over the metal wiring patterns 38 is polished, the first working rate V.sub.P at convex portions 35 of the oxide film 39 is higher than the second working rate V.sub.O at other portions of the oxide film 39 at which no convex portion 35 exists. Consequently, the surface of the oxide film 39 is gradually flattened uniformly as shown in FIG. 7B. In the conventional flattening polishing method, it must be noted that the portion of the oxide film 39 on which no convex portion 35 is present is also removed at the second working rate V.sub.O and that the time required for flattening the convex portions 35 on the surface of the oxide film 39 depends upon the relative working rate V.sub.P /V.sub.O of the first working rate V.sub.P to the second working rate V.sub.O. In other words, it should be noted that, as the relative working rate V.sub.P /V.sub.O increases, the convex portions 35 are removed in a shorter time by polishing to make the surface of the oxide film 39 smooth.
However, the relative working rate V.sub.P /V.sub.O depends upon the size of the convex portions 35. For example, an experiment in which a BPSG film formed over striped polycrystalline silicon patterns 5,000 .ANG. high and 1 to 25 .mu.m wide was polished through the use of colloidal silica slurry proved that the relative working rate V.sub.P /V.sub.O has a dependency upon the width L of the convex portions 35 as shown in FIG. 8. In particular, the relative working rate V.sub.P /V.sub.O decreases as the width L of the convex portions 35 increases. According to the results of the experiment shown in FIG. 8, (V.sub.P /V.sub.O -1) increases in proportion to L.sup.0.33, and consequently, if the relative working rate V.sub.P /V.sub.O is 20 when, for example, the width L of the convex portions 35 is 1 .mu.m, the relative working rate V.sub.P /V.sub.O will decrease to 10 when the width L of the convex portions 35 increases to 10 .mu.m, and the relative working rate V.sub.P /V.sub.O will decrease to approximately 3 when the width L of the convex portions 35 increases to 500 .mu.m.
The fact that the relative working rate V.sub.P /V.sub.O depends upon the size of the convex portions 35 means that the surface flattening rate by polishing depends upon the size of the convex portions 35. In particular, when first to third metal wiring patterns 38.sub.1 -38.sub.3 having different widths are formed over the silicon substrate 30 with a device layer 31 interposed therebetween as shown in FIG. 9A, first to third convex portions 35.sub.1 -35.sub.3 having different widths are also produced on the oxide film 39 formed over the first to third metal wiring patterns 38.sub.1 -38.sub.3. A relationship of V.sub.O &lt;V.sub.3 &lt;V.sub.2 &lt;V.sub.1 holds where V.sub.O represents the working rate at portions of the oxide film 39 at which the first to third convex portions 35.sub.1 -35.sub.3 are not present and V.sub.1, V.sub.2 and V.sub.3 represent the working rates at the portions of the oxide film 39 at which the first to third convex portions 35.sub.1 -35.sub.3 are produced, respectively. Accordingly, even if the portion of the oxide film 39 at the first convex portion 35.sub.1 is flattened as shown in FIG. 9B after the passage of a time t.sub.1 after starting working, the portions of the oxide film 39 at the second and third convex portions 35.sub.2, 35.sub.3 will remain unflattened and offsets will still remain on the oxide film 39. If the working is continued in order to flatten all of the portions of the oxide film 39 at the second and third convex portions 35.sub.2, 35.sub.3, the oxide film 39 will removed entirely at the portion of the oxide film 39 at the first convex portion 35.sub.1, exposing the first metal wiring pattern 38.sub.1 as shown in FIG. 9C. Accordingly, the conventional flattening polishing method has a problem in that the optimization of the working time is very difficult where convex portions of various sizes are present, as is the actual case for the surface of a semiconductor device in which semiconductor integrated circuits are formed over a semiconductor substrate.
In addition, because the efficiency in flattening decreases as the size of the convex portions 35 increases, problems are encountered in practical use. For example, a 64 Mb DRAM has a structure wherein a memory cell area R.sub.memory about 460 .mu.m wide and a perimetric circuit area R.sub.perimeter about 50 .mu.m wide are repeated regularly. As shown in FIG. 10, stacked capacitor cells 45 approximately 5,000 to 8,000 .ANG. high are formed in a concentrated manner in the memory cell area R.sub.memory while such elements as capacitor plate wiring lines and sense amplifiers are formed in the perimetric circuit area R.sub.perimeter. In the 64 Mb DRAM having the construction described above, if a BPSG film 44 is grown and reflowed, the surface of the BPSG film 44 will be flattened in both the memory cell area R.sub.memory and the perimetric circuit area R.sub.perimeter, but the entire memory cell area R.sub.memory will exhibit a smoothly swollen condition with respect to the perimetric circuit area R.sub.perimeter. The large offset h between the memory cell area R.sub.memory and the perimetric circuit area R.sub.perimeter after a reflow condition has been entered complicates the formation of an aluminum wiring pattern on the BPSG film 44. Incidentally, even if an attempt is made to remove the initial offset h.sub.O by the conventional flattening polishing method, since the convex region in the memory cell area R.sub.memory is large, the relative working rate V.sub.memory /V.sub.perimeter of the working rate V.sub.memory in the memory cell area R.sub.memory to the working rate V.sub.perimeter in the flattened perimetric circuit area R.sub.perimeter will not reach a high level, preventing the efficient removal of the initial offset h.sub.O. Further, if the working is continued, the film thickness h.sub.BP ' of the BPSG film 44 in the perimetric circuit area R.sub.perimeter after a reflow condition has been entered may possibly be decreased excessively.
Since flattening of the surface of an oxide film by polishing depends in this way upon the local distribution of the working pressure corresponding to the unevenness of the surface of the oxide film, the conventional flattening polishing method has a serious problem in that the surface flattening rate decreases as the size of a convex portion increases and it is difficult to flatten the entire surface area of the semiconductor device in which semiconductor integrated circuits constituted from patterns of various sizes are formed over a semiconductor substrate.
Second Subject: Dispersion in Working Amount of Substrate in Its Plane
The conventional flattening polishing method employing colloidal silica slurry commonly provides a working rate distribution in which the working rate in a peripheral portion of a wafer is higher by 5 to 10% than the working rate at a central portion of the wafer. For example, when polishing a BPSG film 54 formed over a silicon substrate 50 with a device layer 51 interposed therebetween and having initial thickness t.sub.O as shown in FIG. 11, the film thickness t.sub.perimeter of the BPSG film 54 in the perimetric area R.sub.perimeter will become thinner than the film thickness t.sub.center of the BPSG film 54 in the central area R.sub.center. An offset present in the perimetric area R.sub.perimeter will naturally also become thinner than another offset present in the central area R.sub.center. In this manner, with the conventional flattening polishing method, a substrate in-plane distribution is naturally caused in the film thickness of the BPSG film 54 and the offsets on the surface of the BPSG film 54 which complicates the dry etching for formation of contact holes after polishing. In particular, the dispersion of the working amount of a silicon substrate in its plane and the dispersion of the flattening efficiency create problems which become increasingly significant in practical use as the diameter of a silicon substrate used increases.
Third Subject: Metal Pollution of the Device Layer
When the mirror surface polishing is performed through the use of colloidal silica slurry for a semiconductor device in which no device layer is formed over a silicon substrate, the metal pollution of the silicon substrate can be fully eliminated, even for cases in which alkali metal or transition metal is contained in the particles of the colloidal silica or in the medium in which the colloidal silica particles are dispersed, by etching the surface of the semiconductor device by several .mu.m after polishing. Generally, a very small amount (several ppm or so) of Na is contained in the colloidal silica particles or in a medium in which the colloidal silica particles are dispersed. However, when polishing is employed to flatten the surface of an interlayer insulating film before forming an overlying layer of metal wiring lines, there is a danger of excessively reducing the thickness of the interlayer insulating film. Excessive reduction of the thickness of this film may allow alkali metal or transition metal to penetrate the interlayer insulating film and shift the threshold voltage of a MOSFET in the device layer. A gettering layer may be employed to block polluting substances such as Na when forming the interlayer insulating layer, but the conventional flattening polishing method does not take this factor into consideration at all.